The present invention relates to integrated circuits and the manufacturing of semiconductor devices. More particularly, the invention provides a semiconductor device having a transistor and method for fabricating thereof. Merely by way of example, the invention has been applied to a junction-less field effect transistor having a fin structure.
Semiconductor technology has been evolved to achieve higher device density, higher performance and lower costs. In order to achieve high complexity and circuit density, three-dimensional designs and nano-technology processes have been developed. As an example, a field-effect transistor (FET) has been designed to have a fin protruded from the substrate. Although a fin-FET device to a certain extent reduces snort channel effects and increases a drive current, however, it suffers high parasitic resistance associated with the high drive current.
A junction-less transistor structure undoubtedly provides a new way for further improving performance of semiconductor devices. The structure of a junction-less transistor device differs from conventional semiconductor structures, in which there is no junction between the channel region and the associated source and drain regions. Comparing with conventional junction-type transistors, a junction-less transistor includes a source, a drain, and a channel that have a same doping polarity (interchangeably used as conductivity type hereinafter). In other words, junction-less means that the channel lacks a doped p-n junction in the boundary of the transistor. The channel may contain higher or lower doped regions of the same conductivity type (doping polarity) as the source and drain. A junction-less semiconductor device can have better performance than conventional junction transistor devices.
Examples of conventional junction-less transistor devices are shown in FIGS. 1A and 1B. FIG. 1A shows a junction-less transistor device formed on the bulk silicon substrate. The transistor device includes a doped semiconductor material layer 140′ on a substrate 110′, a gate electrode structure 154′ is disposed on semiconductor material layer 140′, the gate electrode structure 154′ surrounds a portion of the semiconductor material layer 140′, source/drain structures 160′ are formed in the semiconductor material layer 140′ at opposite sides of the gate structure 154′.
FIG. 1B shows a junction-less transistor device formed on a silicon-on-insulator (SOI). As shown, an insulating layer 120′ is formed over a substrate 110′, a doped semiconductor material layer 140′ is formed on the insulating layer 120, a gate electrode structure 154′ surrounds a portion of semiconductor material layer 140′, and source/drain structures 160′ are formed in the semiconductor material layer 140′ at opposite sides of the gate structure 154′.
Although these two prior art structures improve the performance of semiconductor devices, they do have some problems. For example, as shown in FIG. 1A, the source/drain structures are in contact with the bulk silicon substrate, resulting in a high capacitance value of the contact region. As in the case of the structure shown in FIG. 1B, the presence of the insulating layer causes a substantial increase in self-heating of the device.
Therefore, it is desirable to have improved structures of junction-less transistor devices and method for fabricating the devices.